Eur. Phys. J. Special Topics 228, 2269-2285 (2019)
https://doi.org/10.1140/epjst/e2019-900042-x

Regular Article

Sklansky tree adder realization in 1S1R resistive switching memory architecture

¹ Institut für Werkstoffe der Elektrotechnik II (IWE II), RWTH Aachen University, Sommerfeldstr. 24, 52074 Aachen, Germany
² JARA – Fundamentals for Future Information Technology, 52425 Jülich, Germany
³ Peter Grünberg Institut 7 (PGI-7), Forschungszentrum Jülich GmbH, 52425 Jülich, Germany
⁴ School of Computer Science and Engineering, Nanyang Technological University, 639798, Singapore, Singapore

^a e-mail: siemon@iwe.rwth-aachen.de

Received: 15 February 2019
Received in final form: 20 May 2019
Published online: 14 October 2019

Abstract

Redox-based resistive switches are an emerging class of non-volatile memory and logic devices. Especially, ultimately scaled transistor-less passive crossbar arrays using a selector/resistive-switch (1S1R) configuration are one of the most promising architectures. Due to the scalability and the inherent logic and memory capabilities of these devices, they are good candidates for logic-in-memory approaches. But due to the memory architecture, true parallelism can only be achieved by either working on several arrays at the same time or at multiple lines in an array at the same time. In this work, a Sklansky tree adder is presented, which exploits the parallelism of a single crossbar array. The functionality is proven by means of memristive simulations using a physics-based TaO_x model. The circuit and device requirements for this approach are discussed.